A fault simulation method: Parallel pattern critical path tracing
- 1 August 1993
- journal article
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 4 (3) , 255-265
- https://doi.org/10.1007/bf00971974
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The parallel-test-detect fault simulation algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The dynamic reduction of fault simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Parallel pattern fault simulation based on stem faults in combinational circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A method of fault simulation based on stem regionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Accelerated Fault Simulation and Fault Grading in Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- An Algorithm for the Generation of Test Sets for Combinational Logic NetworksIEEE Transactions on Computers, 1975
- A Deductive Method for Simulating Faults in Logic CircuitsIEEE Transactions on Computers, 1972
- Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsIEEE Transactions on Electronic Computers, 1967