"Depletion isolation effect" of surrounding gate transistors
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 44 (12) , 2303-2305
- https://doi.org/10.1109/16.644659
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A scalable low power vertical memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Performance of the 3-D PENCIL flash EPROM cell and memory arrayIEEE Transactions on Electron Devices, 1995
- Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA)IEEE Transactions on Electron Devices, 1992
- Impact of surrounding gate transistor (SGT) for ultra-high-density LSI'sIEEE Transactions on Electron Devices, 1991
- Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuitsIEEE Transactions on Electron Devices, 1991
- Two-dimensional simulation and measurement of high-performance MOSFETs made on a very thin SOI filmIEEE Transactions on Electron Devices, 1989
- Subthreshold slope of thin-film SOI MOSFET'sIEEE Electron Device Letters, 1986