FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 564-572
- https://doi.org/10.1109/test.1991.519719
Abstract
No abstract availableKeywords
This publication has 17 references indexed in Scilit:
- Fault modeling and testing generation for sample-and-hold circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A framework for design and testing of analog integrated circuitsIEEE Transactions on Instrumentation and Measurement, 1990
- Matching properties of MOS transistorsIEEE Journal of Solid-State Circuits, 1989
- Design for testability of analog/digital networksIEEE Transactions on Industrial Electronics, 1989
- Realistic fault modeling for VLSI testingPublished by Association for Computing Machinery (ACM) ,1987
- Yield Simulation for Integrated CircuitsPublished by Springer Nature ,1987
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Modeling of Lithography Related Yield Losses for CAD of VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Statistical Simulation of the IC Manufacturing ProcessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1982
- An integrated-circuit comparator macromodelIEEE Journal of Solid-State Circuits, 1976