An algorithm to test reconfigured RAMs

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Abstract
State-of-the-art RAM chips are invariably reconfigurable. After reconfiguration, the logical neighborhood of the memory cells may no longer be same as the physical neighborhood. Test algorithms used after reconfiguration to detect physical neighborhood faults have to consider that (i) the physical and logical neighborhoods are different and (ii) the address mapping of the reconfigured RAM is no longer available. Another reason for distinct logical and physical neighborhoods is address line scrambling, done to minimize the silicon area and the critical path lengths. We present a test algorithm to detect 5-cell physical neighborhood pattern sensitive faults in reconfigured RAMs and RAMs with scrambled address lines. This algorithm is based on the widely used MSCAN and Marching tests, and requires only O(N upper bound[log 2 N]) reads and writes to test an N-bit RAM. It also detects other faults such as stuck-at faults, decoder faults, 2-coupling faults, and 3-coupling faults Author(s) Franklin, M. Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA Saluja, K.K.

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