Integration scale increase of processor-arrays by using hierarchical redundancy
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Hierarchical redundancy for orthogonal arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The development of the WASP 3 processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A full experience of designing a wafer scale 2D arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Rotary spare replacement redundancy for tree architecture WSIsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A defect and fault tolerant design of WSI static RAM modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fault-Tolerant k-out-of-n Logic Unit Network with Minimum InterconnectionPublished by Springer Nature ,1990
- Reconfiguration of VLSI/WSI mesh array processors with two-level redundancyIEEE Transactions on Computers, 1989
- Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arraysIEEE Transactions on Computers, 1988
- Fault Tolerance Techniques for Array Structures Used in SupercomputingComputer, 1986
- A 4-Mbit full-wafer ROMIEEE Transactions on Electron Devices, 1980