How many logic levels does floating-point addition require?
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 142-149
- https://doi.org/10.1109/iccd.1998.727035
Abstract
We present an algorithm for IEEE floating-point addition. The latency of the addition algorithm for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. The algorithm accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly rounded sum/difference in the format required by the IEEE Standard. The presentation of the algorithm is technology independent and can serve as basis for evaluation and comparison with other floating-point addition algorithmsKeywords
This publication has 7 references indexed in Scilit:
- The SNAP project: design of floating point arithmetic unitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Pipelined packet-forwarding floating point. II. An adderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A dual mode IEEE multiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On the design of IEEE compliant floating point unitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 167 MHz radix-4 floating point multiplierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A reduced-area scheme for carry-select addersIEEE Transactions on Computers, 1993
- Design of the IBM RISC System/6000 floating-point execution unitIBM Journal of Research and Development, 1990