A structure and technique for pseudorandom-based testing of sequential circuits
- 1 February 1995
- journal article
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 6 (1) , 107-115
- https://doi.org/10.1007/bf00993133
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- ScanBist A Multi-frequency Scan-Based BIST MethodPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A complexity analysis of sequential ATPGPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Hardware-based weighted random pattern generation for boundary scanPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Multiple distributions for biased random test patternsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- FREEZE: a new approach for testing sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new procedure for weighted random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Non-scan design-for-testability techniques for sequential circuitsPublished by Association for Computing Machinery (ACM) ,1993
- Circular self-test path: a low-cost BIST techniquePublished by Association for Computing Machinery (ACM) ,1987
- Design for testability—A surveyProceedings of the IEEE, 1983