Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 0.4 micron fully complementary BiCMOS technology for advanced logic and microprocessor applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Three-dimensional transient electrothermal simulation of electrostatic discharge protection circuitsJournal of Electrostatics, 1995
- ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-μm channel length CMOS technologiesIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1995
- Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technologyJournal of Electrostatics, 1994
- Designing on-chip power supply coupling diodes for ESD protection and noise immunityJournal of Electrostatics, 1994
- Integrated circuit metal in the charged device model: bootstrap heating, melt damage, and scaling lawsJournal of Electrostatics, 1993
- Shallow trench isolation double-diobe electrostatic discharge circuit and interaction with DRAM output circuitryJournal of Electrostatics, 1993
- On the proportioning of chip area for multistage Darlington power transistorsIEEE Transactions on Electron Devices, 1976
- Pulse Power Failure Modes in SemiconductorsIEEE Transactions on Nuclear Science, 1970