ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-μm channel length CMOS technologies
- 1 June 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A
- Vol. 18 (2) , 303-313
- https://doi.org/10.1109/95.390308
Abstract
No abstract availableKeywords
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