Fault detection and fault localization using I/sub DDQ/-testing in parallel testable FAST-SRAMs
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- CIRCUIT DESIGN FOR BUILT-IN CURRENT TESTINGPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Associative search based test algorithms for test acceleration in FAST-RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A current testing for CMOS static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Modeling of intra-cell defects in CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Using march tests to test SRAMsIEEE Design & Test of Computers, 1993
- A new testing acceleration chip for low-cost memory testsIEEE Design & Test of Computers, 1993
- Test generation for current testing (CMOS ICs)IEEE Design & Test of Computers, 1990
- Flag-algebra: a new concept for the realisation of fully parallel associative architecturesIEE Proceedings E Computers and Digital Techniques, 1989