Test generation for path delay faults using binary decision diagrams
- 1 March 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 44 (3) , 434-447
- https://doi.org/10.1109/12.372035
Abstract
No abstract availableThis publication has 26 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A method of delay fault test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Delay fault models and test generation for random logic sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Energy minimization based delay testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Boolean algebraic test generation using a distributed systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Logic systems for path delay test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient implementation of a BDD packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Delay-fault test generation and synthesis for testability under a standard scan design methodologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Test generation and verification for highly sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981