A 46-ns 1-Mbit CMOS SRAM
- 1 February 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (1) , 53-58
- https://doi.org/10.1109/4.256
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- 25-ns 256K×1/64K×4 CMOS SRAM'sIEEE Journal of Solid-State Circuits, 1986
- A 1-Mbit CMOS dynamic RAM with design-for test functionsIEEE Journal of Solid-State Circuits, 1986
- A 25ns 256K CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A 45-ns 256K CMOS static RAM with a tri-level word lineIEEE Journal of Solid-State Circuits, 1985
- A 256K CMOS SRAM with variable impedance data-line loadsIEEE Journal of Solid-State Circuits, 1985
- A 20 ns 64K CMOS static RAMIEEE Journal of Solid-State Circuits, 1984
- A low power 46 ns 256 kbit CMOS static RAM with dynamic double word lineIEEE Journal of Solid-State Circuits, 1984
- A high-speed Hi-CMOSII 4K static RAMIEEE Journal of Solid-State Circuits, 1981