A 20 ns 64K CMOS static RAM
- 1 December 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (6) , 1008-1013
- https://doi.org/10.1109/jssc.1984.1052259
Abstract
A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3 /spl mu/m design rule are used. Good RAM performance is achieved by use of a pulsed-word-line technique and double p-well bipolar-CMOS circuitry.Keywords
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