RSYN: a system for automated synthesis of reliable multilevel circuits

This publication has 15 references indexed in Scilit:

• Design and synthesis of self-checking VLSI circuits and systems
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Design and synthesis of self-checking VLSI circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
• Can test length be reduced during synthesis process?
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• A synthesis and optimization procedure for fully and easily testable sequential machines
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
• MIS: A Multiple-Level Logic Optimization System
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• Concurrent error detection in highly structured logic arrays
  IEEE Journal of Solid-State Circuits, 1987
• Concurrent Error Detection and Testing for Large PLA's
  IEEE Journal of Solid-State Circuits, 1982
• Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
  IEEE Transactions on Computers, 1980
• Error-Control Techniques for Logic Processors
  IEEE Transactions on Computers, 1972
• The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design
  IEEE Transactions on Computers, 1971