Deterministic BIST with multiple scan chains

This publication has 18 references indexed in Scilit:

• GENERATION OF VECTOR PATTTERNS THROUGH RESEEDING OF MUETIPLE-POLYNOMIAL LINEAR FEEDBACK SHIFT REGIST
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Hardware-based weighted random pattern generation for boundary scan
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Generating pseudo-exhaustive vectors for external testing
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Using BIST control for pattern generation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Pattern generation for a deterministic BIST scheme
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Optimal configuring of multiple scan chains
  IEEE Transactions on Computers, 1993
• Design considerations for Parallel pseudoRandom Pattern Generators
  Journal of Electronic Testing, 1990
• Scan-path architecture for pseudorandom testing
  IEEE Design & Test of Computers, 1989
• Pseudorandom Arrays for Built-In Tests
  IEEE Transactions on Computers, 1986
• Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test
  IBM Journal of Research and Development, 1983