Location and identification for single and multiple faults in testable redundant PLAs for yield enhancement

13 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 670-678
https://doi.org/10.1109/test.1989.82354

Abstract

The authors present the basic structure of a testable and repairable programmable logic array (PLA) and the design modifications which are required for a full diagnosis and yield enhancement. The testing process is fully analyzed, and the conditions for diagnosis are presented. It is proved that identification in the presence of multiple (crosspoint, stuck-at, and bridging) faults is possible with high coverage. The criteria which permit diagnosis are based on a hierarchical organization of the testing process; significant improvements over previous redundant structures can be achieved. This results in a compact structure with a homogeneous layout which has been evaluated with respect to area overhead for VLSI implementation. Simulation results for benchmark devices are presented. These suggest that an efficient repair of VLSI PLAs for yield enhancement can be achieved.<>

Keywords

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