Automated test pattern generation for analog integrated circuits
- 22 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specified by the user and determines optimal test signals that maximize the detectability of all faults. As statistical fluctuations have to be considered when evaluating analog circuits, it is based on a statistical test criterion. Two examples demonstrate the practical use and versatility of this approach.Keywords
This publication has 9 references indexed in Scilit:
- Testing Of Analog Systems Using Behavioral Models And Optimal Experimental Design TechniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Analytical Fault Modeling And Static Test Generation For Analog ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Fault Detection And Input Stimulus Determination For The Testing Of Analog Integrated Circuits Based On Power-supply Current MonitoringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- L/sup 2/RFM-local layout realistic faults mapping scheme for analogue integrated circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dynamic test signal design for analog ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Matching properties of MOS transistorsIEEE Journal of Solid-State Circuits, 1989
- Realistic Yield Simulation for VLSIC Structural FailuresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Characterisation and modeling of mismatch in MOS transistors for precision analog designIEEE Journal of Solid-State Circuits, 1986
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986