A large-signal equivalent circuit model for substrate-induced drain-lag phenomena in HJFETs
- 1 September 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 43 (9) , 1336-1342
- https://doi.org/10.1109/16.535316
Abstract
A large-signal HJFET model is developed for drain-lag phenomena caused by deep traps beneath the channel. The model is based on the self-backgating and Shockley-Read-Hall (SRH) statistics. It is shown by two-dimensional (2D) device simulation that electron capture in deep traps is much faster than electron emission under large-signal conditions; therefore, drain current exhibits different responses for rising and falling steps of applied voltage. In the circuit model, electron capture and emission in deep traps are expressed by a parallel circuit consisting of a diode and a resistor, which are physically deduced from SRH statistics. The model agrees well with the 2D simulation results and experimental current-transient data for large-signal voltage steps. In addition, this model accurately describes small-signal drain-conductance dispersion and temperature effects on the trapping phenomena.Keywords
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