Abstract
This paper describes a structured test re-use methodologyand infrastructure for core-based system chips. The methodologyis based on the use of a structured test bus frameworkthat provides access to virtual components in asystem chip allowing the test methodologies and test vectorsfor these components to be re-used. It addresses thetest access, isolation, interconnect and shadow logic testproblems without requiring modifications to the components,even for cores with more ports than chip pins. Thetest area overhead required, including test bus routing, toimplement this methodology can be less than 1%.

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