New planarisation process for low current, high-speedInP/InGaAsheterojunction bipolar transistors

1 February 1996

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 32 (3) , 266-267
https://doi.org/10.1049/el:19960154

Abstract

Low current, high-speed InP/InGaAs heterojunction bipolar transistors were fabricated using a silicon nitride based planarisation process. Realised devices offered cutoff frequencies of >100 GHz and a DC current gain of >50 at a collector current of only 2 mA. The best maximum frequency of oscillation was 195 GHz. It is also demonstrated that the new planarisation process offers a proper base for the fabrication of integrated circuits. These results increase the competitiveness of InP-based HBTs for high-speed, low power applications.

Keywords

This publication has 7 references indexed in Scilit:

InGaAs/InP heterojunction bipolar transistor grownby all-solid source molecular beam epitaxy
Electronics Letters, 1995
All solid source molecular beam epitaxy growth of1.35 µm wavelengthstrained-layer GaInAsP quantum well laser
Electronics Letters, 1995
Ultra-high-speed InP/InGaAs heterojunction bipolar transistors
IEEE Electron Device Letters, 1994
High-performance Zn-doped-base InP/InGaAs double-heterojunction bipolar transistors grown by metalorganic vapor phase epitaxy
Applied Physics Letters, 1994
High-speed InP/InGaAs heterojunction bipolar transistors
IEEE Electron Device Letters, 1993
InP/InGaAs double-heterojunction bipolar transistor with step-graded InGaAsP collector
Electronics Letters, 1993
Subpicosecond InP/InGaAs heterostructure bipolar transistors
IEEE Electron Device Letters, 1989