A taxonomy of reconfiguration techniques for fault-tolerant processor arrays
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 23 (1) , 55-69
- https://doi.org/10.1109/2.48799
Abstract
Focuses on the characterization and classification of reconfiguration techniques. The techniques are differentiated according to the type of redundancy (time or hardware), allocation of redundancy (local or global), replacement unit, (processor or a set of processors), switching domain (global or local), and switching implementation (switching element, bus, or network). Typical techniques from four major classes-set switching, processor switching, local redundancy, and time redundancy-are reviewed. The proposed taxonomy can be used as a guide for future research in design and analysis of reconfiguration schemes.Keywords
This publication has 17 references indexed in Scilit:
- A general index mapping technique for array reconfigurationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fault-tolerant array processors using single-track switchesIEEE Transactions on Computers, 1989
- On the Analysis and Design of Hierarchical Fault-Tolerant Processor ArraysPublished by Springer Nature ,1989
- Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-D ArraysPublished by Springer Nature ,1989
- Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arraysIEEE Transactions on Computers, 1988
- Fault Tolerance Techniques for Systolic ArraysComputer, 1987
- Techniques for implementing two-dimensional wafer-scale processor arraysIEE Proceedings E Computers and Digital Techniques, 1987
- Gracefully Degradable Processor ArraysIEEE Transactions on Computers, 1985
- The Diogenes Approach to Testable Fault-Tolerant Arrays of ProcessorsIEEE Transactions on Computers, 1983
- Design of a Massively Parallel ProcessorIEEE Transactions on Computers, 1980