Low overhead fault-tolerant FPGA systems
- 1 June 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 6 (2) , 212-221
- https://doi.org/10.1109/92.678870
Abstract
Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's). The physical design is partitioned into a set of tiles. In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile. Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.Keywords
This publication has 19 references indexed in Scilit:
- Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An approach for testing programmable/configurable field programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fault covers in reconfigurable PLAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 30-ns 64-Mb DRAM with built-in self-test and self-repair functionIEEE Journal of Solid-State Circuits, 1992
- Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyondIEEE Journal of Solid-State Circuits, 1991
- On the design of a redundant programmable logic array (RPLA)IEEE Journal of Solid-State Circuits, 1987
- A review of fault-tolerant techniques for the enhancement of integrated circuit yieldProceedings of the IEEE, 1986
- Configuration of VLSI Arrays in the Presence of DefectsJournal of the ACM, 1984
- Fault-Tolerant Semiconductor MemoriesComputer, 1984
- A study of the data commutation problems in a self-repairable multiprocessorPublished by Association for Computing Machinery (ACM) ,1968