High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Electrical properties and detection methods for CMOS IC defectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test generation for current testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Test generation for sequential circuits using individual initial value propagationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing oriented analysis of CMOS ICs with opensPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Testing for parametric faults in static CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Mixed-level sequential test generation using a nine-valued relaxation algorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On detecting single and multiple bridging faults in CMOS circuits using the current supply monitoring methodPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test pattern generation for sequential MOS circuits by symbolic fault simulationPublished by Association for Computing Machinery (ACM) ,1989
- Transistor-level test generation for physical failures in CMOS circuitsPublished by Association for Computing Machinery (ACM) ,1986
- Test Generation for MOS Circuits Using D-AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983