Synthesis of Sequential Circuits for Robust Path Delay Fault Testability
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10639667,p. 275-280
- https://doi.org/10.1109/icvd.1993.669696
Abstract
No abstract availableKeywords
This publication has 24 references indexed in Scilit:
- A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Equivalence of robust delay-fault and single stuck-fault test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of multi-level combinational circuits for complete robust path delay fault testabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis of sequential circuits for parallel scanPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Arrangement of latches in scan-path design to improve delay fault coveragePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testability-preserving circuit transformationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Robust delay-fault test generation and synthesis for testability under a standard scan design methodologyPublished by Association for Computing Machinery (ACM) ,1991
- Design of robustly testable combinational logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Scan Design Using Standard Flip-FlopsIEEE Design & Test of Computers, 1987