EOS/ESD reliability of deep sub-micron NMOS protection devices
- 1 January 1995
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We have identified new failure mechanisms in EOS/ESD protection circuits for a 0.35 /spl mu/m technology and investigated the effect of process variations on these circuits. We present strategies to improve the performance of these circuits and prevent premature failure of the devices.Keywords
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