Single-event gate rupture in vertical power MOSFETs; an original empirical expression

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Abstract
An empirical expression is derived that describes the susceptibility of a power double-diffused metal-oxide semiconductor (DMOS) field-effect transistor (FET) to single-event gate rupture (SEGR) induced by the interaction of mono-energetic ions with regions of the n-epi, gate oxide, and polysilicon gate. Using this expression, the failure threshold voltages for the gate and drain can be analytically determined for any particular value of energy deposition along the ion's path or more commonly described as the ion's linear energy transfer (LET) function. This paper delineates our research, an in-depth study of vertical power DMOS transistors, having a 50-nm gate oxide and a strong SEGR response, subjected to various mono-energetic ions, representing particular values of LET between 0 and 83 MeV cm/sup 2/ mg/sup -1/. A description of the devices characterized, the test setup and test methodology employed, the failure threshold voltages measured, and the analysis techniques used are all summarized. Finally, an empirical equation is presented that portrays the locus of SEGR in the {-V/sub GS/, V/sub DS/} plane for all values of LET.

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