Transforming sequential logic in digital CMOS ICs for voltage and I/sub DDQ/ testing
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 361-365
- https://doi.org/10.1109/edtc.1994.326851
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Extraction and simulation of realistic CMOS faults using inductive fault analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Current vs. logic testability of bridges in scan chainsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CMOS bridging fault detectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design of ICs applying built-in current testingJournal of Electronic Testing, 1992
- I DDQ testing in CMOS digital ASICsJournal of Electronic Testing, 1992
- I DDQ testing: A reviewJournal of Electronic Testing, 1992
- Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- A CMOS fault extractor for inductive fault analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Test Considerations for Gate Oxide Shorts in CMOS ICsIEEE Design & Test of Computers, 1986
- Design for testability—A surveyProceedings of the IEEE, 1983