Defect-tolerant hypercube architectures using hierarchical redundancy

This publication has 10 references indexed in Scilit:

• Integration scale increase of processor-arrays by using hierarchical redundancy
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Enhanced hypercubes
  IEEE Transactions on Computers, 1991
• Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection
  Published by Springer Nature ,1990
• Universal Fault‐Tolerant Hypercube Architecture without a Switching Mechanism
  Systems and Computers in Japan, 1990
• A taxonomy of reconfiguration techniques for fault-tolerant processor arrays
  Computer, 1990
• Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays
  IEEE Transactions on Computers, 1988
• Fault Tolerance Techniques for Array Structures Used in Supercomputing
  Computer, 1986
• Generalized Hypercube and Hyperbus Structures for a Computer Network
  IEEE Transactions on Computers, 1984
• The cube-connected cycles: a versatile network for parallel computation
  Communications of the ACM, 1981
• Communication Structures for Large Networks of Microcomputers
  IEEE Transactions on Computers, 1981