Logic testing of bridging faults in CMOS integrated circuits
- 1 March 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 47 (3) , 338-345
- https://doi.org/10.1109/12.660170
Abstract
We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports fault coverage as well as defect coverage for the MCNC layouts of the ISCAS-85 benchmark circuits.Keywords
This publication has 21 references indexed in Scilit:
- AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATORPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Test Pattern Generation for Realistic Bridge Faults in CMOS ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Carafe: an inductive fault analysis tool for CMOS VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholdsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Diagnosis of realistic bridging faults with single stuck-at informationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test pattern generation using Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- E-PROOFS: A CMOS bridging fault simulatorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Physically realistic fault models for analog CMOS neural networksIEEE Journal of Solid-State Circuits, 1991
- A CMOS fault extractor for inductive fault analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Bridging and Stuck-At FaultsIEEE Transactions on Computers, 1974