Using ILA testing for BIST in FPGAs
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present an improved Built-In Self-Test (BIST) approach for the programmable logic blocks (PLBs) of a Field Programmable Gate Array (FPGA), which repeatedly reconfigures the FPGA as a group of C-testable iterative logic arrays. The new architecture is easily scalable with increasing size of FPGAs and ensures routability of the various configurations required to completely test the FPGA in three test sessions. In addition, the BIST approach addresses RAM mode testing as well as testing the adder/subtractor modes in FPGAs.Keywords
This publication has 19 references indexed in Scilit:
- Easily testable iterative unidimensional CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Incoming inspection of FPGA'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An approach for testing programmable/configurable field programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testing combinational iterative logic arrays for realistic faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Built-in self test for C-testable ILA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- C-Testability of Two-Dimensional Iterative ArraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Built-In Testing of One-Dimensional Unilateral Iterative ArraysIEEE Transactions on Computers, 1984
- Design of Easily Testable Bit-Sliced SystemsIEEE Transactions on Computers, 1981
- A Functional Approach to Testing Bit-Sliced MicroprocessorsIEEE Transactions on Computers, 1981
- Testing for faults in combinational cellular logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967