Short-circuit energy dissipation modeling for submicrometer CMOS gates
- 1 January 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 47 (9) , 1350-1361
- https://doi.org/10.1109/81.883330
Abstract
No abstract availableThis publication has 24 references indexed in Scilit:
- Accurate evaluation of CMOS short-circuit power dissipation for short-channel devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A comprehensive delay macro modeling for submicrometer CMOS logicsIEEE Journal of Solid-State Circuits, 1999
- A novel macromodel for power estimation in CMOS structuresIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
- Power consumption estimation in CMOS VLSI chipsIEEE Journal of Solid-State Circuits, 1994
- Modeling the "Effective capacitance" for the RC interconnect of CMOS gatesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Short-circuit power dissipation estimation for CMOS logic gatesIEEE Transactions on Circuits and Systems I: Regular Papers, 1994
- A simple MOSFET model for circuit analysisIEEE Transactions on Electron Devices, 1991
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Accurate simulation of power dissipation in VLSI circuitsIEEE Journal of Solid-State Circuits, 1986
- Modeling and simulation of insulated-gate field-effect transistor switching circuitsIEEE Journal of Solid-State Circuits, 1968