Exploiting hysteresis in a CMOS buffer
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 205-208
- https://doi.org/10.1109/icecs.1999.812259
Abstract
A high drive CMOS buffer circuit characterized by a voltage transfer characteristic (VTC) with low threshold voltages and hysteresis is proposed. The proposed circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty. Due to the hysteresis characteristic of this buffer, a comparison with a Schmitt-trigger is provided. An important application of this circuit is the restoration of slow transitioning signals propagated along an RC interconnect. ...Keywords
This publication has 9 references indexed in Scilit:
- A high speed CMOS buffer for driving large capacitive loads in digital ASICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Repeater insertion to reduce delay and power in RC tree structuresPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Repeater design to reduce delay and power in resistive interconnectIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998
- Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive LoadAnalog Integrated Circuits and Signal Processing, 1997
- A unified design methodology for CMOS tapered buffersIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
- Design of tapered buffers with local interconnect capacitanceIEEE Journal of Solid-State Circuits, 1995
- Optimum buffer circuits for driving long uniform linesIEEE Journal of Solid-State Circuits, 1991
- CMOS tapered bufferIEEE Journal of Solid-State Circuits, 1990
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987