On calculating efficient LFSR seeds for built-in self test
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial LFSR TPG. The size of the LFSR, the primitive feedback polynomial and the length of the generated test sequence are a priori known. The method uses a deterministic test cube compression technique and produces a one-seed LFSR test sequence of a predefined test length that achieves high fault coverage. This technique can be applied either in pseudo-random testing for BISTed circuits containing few random resistant faults, or in pseudo-deterministic BIST where it allows the hardware generator overhead area to be reduced. Compared with existing methods, the proposed technique is able to deal with combinational circuits of great size and with a lot of primary inputs. Experimental results demonstrate the effectiveness of our method.Keywords
This publication has 15 references indexed in Scilit:
- An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift RegistersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- GENERATION OF VECTOR PATTTERNS THROUGH RESEEDING OF MUETIPLE-POLYNOMIAL LINEAR FEEDBACK SHIFT REGISTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Test embedding with discrete logarithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new procedure for weighted random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A ring architecture strategy for BIST test pattern generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Timing-driven test point insertion for full-scan and partial-scan BISTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A novel pattern generator for near-perfect fault-coveragePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis of mapping logic for generating transformed pseudo-random patterns for BISTPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Circular self-test path: a low-cost BIST technique for VLSI circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Critical Path Tracing: An Alternative to Fault SimulationIEEE Design & Test of Computers, 1984