Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10893539,p. 674-682
- https://doi.org/10.1109/test.1995.529897
Abstract
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while minimizing area overhead. For a given pseudo-random pattern generator and circuit under test, there are many possible mapping functions that will provide a desired fault coverage for a given test length. This paper formulates the problem of finding a mapping function that can be implemented with a small number of gates as a one of finding a minimum rectangle cover in a binate matrix. A procedure is described for selecting a mapping function and synthesizing mapping logic to implement it. Experimental results for the procedure are compared with published results for other methods. It is shown that by performing iterative global operations, the procedure described in this paper generates mapping logic that requires less hardware overhead to achieve the same fault coverage for the same test length.Keywords
This publication has 18 references indexed in Scilit:
- How To Do Weighted Random Testing For Bist?Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Generation of optimized single distributions of weights for random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automated logic synthesis of random pattern testable circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new procedure for weighted random built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An experimental chip to evaluate test techniques experiment resultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- COMPACTEST: a method to generate compact test sets for combinational circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Circular self-test path: a low-cost BIST technique for VLSI circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-TestIBM Journal of Research and Development, 1983
- The Weighted Random Test-Pattern GeneratorIEEE Transactions on Computers, 1975