A detailed analysis of CMOS SRAM's with gate oxide short defects
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (10) , 1543-1550
- https://doi.org/10.1109/4.634662
Abstract
— Using a model of gate oxide short defects, pre- viously developed and validated experimentally, we investigate the behavior of CMOS SRAM memories,having this defect. Faulty behaviors caused by gate oxide shorts are characterized classifying those that may,cause a logic malfunction and those that degrade the memory,operation without causing a logic error. Merits of SRAM test algorithms to detect gate oxide shorts are analyzed, identifying which are effective in terms of coverage and test cost. Index Terms— Defect modeling, logic testing, parametric test-Keywords
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