Behavioral synthesis for testability
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A synthesis for testability approach is presented. In this approach test points or flip-flops to be used in test point insertion or partial scan to enhance circuit testability are selected. The selection is based on circuit behavioral information rather than low level structural description. This allows test point insertion or partial scan usage on circuits described as interconnections of high level modules. Test statement insertion is also proposed as an alternative to test point insertion and to partial scan. The major advantage of using test statement insertion is a lower pin count and lower test application time overhead than test point insertion and partial scan. The tool has been implemented in a computer program.<>Keywords
This publication has 11 references indexed in Scilit:
- TIGER: testability insertion guidance expert systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An economical scan design for sequential logic test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An incomplete scan design approach to test generation for sequential machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Beta: behavioral testability analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Polynomial complexity algorithms for increasing the testability of digital circuits by testing-module insertionIEEE Transactions on Computers, 1991
- SCOAP: Sandia controllability/observability analysis programPublished by Association for Computing Machinery (ACM) ,1988
- A dynamic programming approach to the test point insertion problemPublished by Association for Computing Machinery (ACM) ,1987
- Design for testability—A surveyProceedings of the IEEE, 1983
- On Modifying Logic Networks to Improve Their DiagnosabilityIEEE Transactions on Computers, 1974
- Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional LogicIEEE Transactions on Computers, 1973