Single-event gate-rupture in power MOSFETs: prediction of breakdown biases and evaluation of oxide thickness dependence
- 1 December 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 42 (6) , 1922-1927
- https://doi.org/10.1109/23.489234
Abstract
Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for V/sub DS/=0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.Keywords
This publication has 9 references indexed in Scilit:
- Single event gate rupture in commercial power MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Impact of oxide thickness on SEGR failure in vertical power MOSFETs; development of a semi-empirical expressionIEEE Transactions on Nuclear Science, 1995
- Evaluation of SEGR threshold in power MOSFETsIEEE Transactions on Nuclear Science, 1994
- Single-event gate rupture in vertical power MOSFETs; an original empirical expressionIEEE Transactions on Nuclear Science, 1994
- A conceptual model of a single-event gate-rupture in power MOSFETsIEEE Transactions on Nuclear Science, 1993
- Breakdown properties of thin oxides in irradiated MOS capacitorsMicroelectronics Reliability, 1993
- Characterization of SiO/sub 2/ dielectric breakdown for reliability simulationIEEE Transactions on Electron Devices, 1993
- Heavy-Ion-Induced, Gate-Rupture in Power MOSFETsIEEE Transactions on Nuclear Science, 1987
- On Heavy Ion Induced Hard-Errors in Dielectric StructuresIEEE Transactions on Nuclear Science, 1987