Bottleneck removal algorithm for dynamic compaction and test cycles reduction
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- A design for testability scheme to reduce test application time in full scanPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On compacting test sets by addition and removal of test vectorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Reduced scan shift: a new testing method for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Dynamic state and objective learning for sequential circuit automatic test generation using recomposition equivalencePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential test generation with reduced test clocks for partial scan designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On generating compact test sequences for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A transitive closure algorithm for test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuitsPublished by Association for Computing Machinery (ACM) ,1993
- Test compaction for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Configuring multiple scan chains for minimum test timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992