I/sub DDQ/ testing and defect classes-a tutorial
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 633-642
- https://doi.org/10.1109/cicc.1995.518262
Abstract
No abstract availableKeywords
This publication has 45 references indexed in Scilit:
- On the detection of delay faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Carafe: an inductive fault analysis tool for CMOS VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Current vs. logic testability of bridges in scan chainsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Test generation with high coverages for quiescent current test of bridging faults in combinational circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Probability analysis for CMOS floating gate faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Residual charge on the faulty floating gate CMOS transistorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- QTAG: a standard for test fixture based I/sub DDQ//I/sub SSQ/ monitorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Analysis of bridging defects in sequential CMOS circuits and their current testabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An experimental study of testing techniques for bridging faults in CMOS ICsIEEE Journal of Solid-State Circuits, 1993
- Quiescent current analysis and experimentation of defective CMOS circuitsJournal of Electronic Testing, 1992