Physical design of testable CMOS digital integrated circuits

This publication has 17 references indexed in Scilit:

• Bottom-up methodology for test preparation and refinement
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Test preparation and fault analysis using a bottom-up methodology
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Bottom-up testing methodology for VLSI
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A methodology for testability enhancement at layout level
  Journal of Electronic Testing, 1991
• Physical design of testable VLSI: techniques and experiments
  IEEE Journal of Solid-State Circuits, 1990
• Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1989
• Test generation of stuck-open faults using stuck-at test sets in CMOS combinational circuits
  Published by Association for Computing Machinery (ACM) ,1989
• A CMOS fault extractor for inductive fault analysis
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
• Optimal layout to avoid CMOS stuck-open faults
  Published by Association for Computing Machinery (ACM) ,1987
• Inductive Fault Analysis of MOS Integrated Circuits
  IEEE Design & Test of Computers, 1985